A technique for outputting the operational result of a cache memory accessible by a central processing unit (CPU) in the process of a simulation of an operation in which the CPU executes a program and computing, based on the operational result, the performance value of the program for the case where the CPU executes the program, has been available (see, for example, Japanese Laid-open Patent Publication No. 2001-249829).
However, in the existing technique, every time an access instruction for instructing the CPU to access a memory area is executed during the simulation of the operation, the operational result of the cache memory is referred to and the performance value of the program is computed. Accordingly, there is a problem that the amount of computation for the performance values of access instructions increases.
In an aspect, the embodiments discussed herein aim to provide a computing apparatus, a computing method, and a computing program capable of reducing the amount of computation.